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Back: Makefile syntax
Forward: Suffix rules
FastBack: Suffix rules
Up: Introducing Makefiles
FastForward: A Minimal GNU Autotools Project
Top: Autoconf, Automake, and Libtool
Contents: Table of Contents
Index: Index
About: About this document

4.3 Macros

A number of useful macros exist which may be used anywhere throughout the `Makefile'. Macros start with a dollar sign, like shell variables. Our first `Makefile' used a few:

$(CC) $(CFLAGS) -c $< -o $@

Here, syntactic forms of `$(..)' are make variable expansions. It is possible to define a make variable using a `var=value' syntax:

CC = ec++

In a `Makefile', $(CC) will then be literally replaced by `ec++'. make has a number of built-in variables and default values. The default value for `$(CC)' is cc.

Other built-in macros exist with fixed semantics. The two most common macros are $@ and $<. They represent the names of the target and the first dependency for the rule in which they appear. $@ is available in any rule, but for some versions of make $< is only available in suffix rules. Here is a simple `Makefile':

all:    dummy
	@echo "$@ depends on dummy"

	touch $@

This is what make outputs when processing this `Makefile':

$ make
touch dummy
all depends on dummy

The GNU Make manual documents these macros in more detail.

This document was generated by Gary V. Vaughan on February, 8 2006 using texi2html

  Published under the terms of the Open Publication License Design by Interspire