It is not necessary to spell out the commands for compiling the
individual C source files, because make can figure them out:
it has an implicit rule for updating a .o file from a
correspondingly named .c file using a gcc -c command.
For example, it will use the command gcc -c main.c -o main.o
to compile main.c into main.o. We can therefore omit the
commands from the rules for the object files.
When a .c file is used automatically in this way, it is also
automatically added to the list of prerequisites. We can therefore omit
the .c files from the prerequisites, provided we omit the commands.
Here is the entire example, with both of these changes, and the variable
objects as suggested above: