System Memory Model
The system memory model defines the semantics of memory operations such as load
and store and specifies how the order in which these operations are issued
by a processor is related to the order in which they reach memory.
The memory model applies to both uniprocessors and shared-memory multiprocessors. Two memory models
are supported: total store ordering (TSO) and partial store ordering (PSO).
Total Store Ordering (TSO)
TSO guarantees that the sequence in which store, FLUSH, and atomic load-store instructions
appear in memory for a given processor is identical to the sequence in
which they were issued by the processor.
Both x86 and SPARC processors support TSO.
Partial Store Ordering (PSO)
PSO does not guarantee that the sequence in which store, FLUSH, and atomic
load-store instructions appear in memory for a given processor is identical to the
sequence in which they were issued by the processor. The processor can reorder
the stores so that the sequence of stores to memory is not the
same as the sequence of stores issued by the CPU.
SPARC processors support PSO; x86 processors do not.
For SPARC processors, conformance between issuing order and memory order is provided by
the system framework using the STBAR instruction. If two of the above instructions
are separated by an STBAR instruction in the issuing order of a processor,
or if the instructions reference the same location, the memory order of the
two instructions is the same as the issuing order. Enforcement of strong data-ordering
in DDI-compliant drivers is provided by the ddi_regs_map_setup(9F) interface. Compliant drivers cannot use the
STBAR instruction directly.
See the SPARC Architecture Manual, Version 9, for more details on the SPARC memory model.